This invention relates to a semiconductor test system for testing semiconductor integrated circuits such as a large scale integrated (LSI) circuit, and more particularly, to a semiconductor test system having an event tester architecture which is capable of testing a mixed signal integrated circuit with high speed and high efficiency. In the semiconductor test system of the present invention, a test system is formed by freely combining a plurality of tester modules having identical or different capabilities where each of the tester module operates independently from one another thereby being able to test an analog signal block and a digital signal block of the device under test at the same time.
FIG. 1 is a schematic block diagram showing an example of a semiconductor test system in the conventional technology for testing a semiconductor integrated circuit (hereafter may also be referred to as xe2x80x9cIC devicexe2x80x9d, xe2x80x9cLSI under testxe2x80x9d or xe2x80x9cdevice under testxe2x80x9d).
In the example of FIG. 1, a test processor 11 is a dedicated processor provided within the semiconductor test system for controlling the operation of the test system through a tester bus. Based on pattern data from the test processor 11, a pattern generator 12 provides timing data and waveform data to a timing generator 13 and a wave formatter 14, respectively. A test pattern is produced by the wave formatter 14 with use of the waveform data from the pattern generator 12 and the timing data from the timing generator 13, and the test pattern is supplied to a device under test (DUT) 19 through a driver 15.
A response signal from the DUT 19 resulted from the test pattern is converted to a logic signal by an analog comparator 16 with reference to a predetermined threshold voltage level. The logic signal is compared with expected value data from the pattern generator 12 by a logic comparator 17. The result of the logic comparison is stored in a failure memory 18 corresponding to the address of the DUT 19. The driver 15, the analog comparator 16 and switches (not shown) for changing pins of the device under test, are provided in a pin electronics 20.
The circuit configuration noted above is provided to each test pin of the semiconductor test system. Therefore, since a large scale semiconductor test system has a large number of test pins, such as from 256 test pins to 1024 test pins, and the same number of circuit configurations each being shown in FIG. 1 are incorporated, an actual semiconductor test system becomes a very large system. FIG. 2 shows an example of outer appearance of such a semiconductor test system. The semiconductor test system is basically formed with a main frame 22, a test head 24, and a work station 26.
The work station 26 is a computer provided with, for example, a graphic user interface (GUI) to function as an interface between the test system and a user. Operations of the test system, creation of test programs, and execution of the test programs are conducted through the work station 26. The main frame 22 includes a large number of test pins (test channels) each having the test processor 11, pattern generator 12, timing generator 13, wave formatter 14 and comparator 17 shown in FIG. 1.
The test head 24 includes a large number of printed circuit boards each having the pin electronics 20 shown in FIG. 1. The test head 24 has, for example, a cylindrical shape in which the printed circuit boards forming the pin electronics are radially aligned. On an upper surface of the test head 24, a device under test 19 is inserted in a test socket at about the center of a performance board 28.
Between the pin electronics circuit and the performance board 28, a pin (test) fixture 27 is provided which is a contact mechanism for communication of electrical signals. The pin fixture 27 includes a large number of contactors such as pogo-pins for electrically connecting the pin electronics circuits and the performance board. The device under test 19 receives a test pattern signal from the pin electronics and produces a response output signal.
In the conventional semiconductor test system, for producing a, test pattern to be applied to a device under test, the test data which is described by, what is called a cycle based format, has been used. In the cycle based format, each variable in the test pattern is defined relative to each test cycle (tester rate) of the semiconductor test system. More specifically, test cycle (tester rate) descriptions, waveform (kinds of waveform, edge timings) descriptions, and vector descriptions in the test data specify the test pattern in a particular test cycle.
In the design stage of the device under test, under a computer aided design (CAD) environment, the resultant design data is evaluated by performing a logic simulation process through a testbench. However, the design evaluation data thus obtained through the testbench is described in an event based format. In the event based format, each change point (event) in the particular test pattern, such as from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d or from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, is described with reference to a time passage. The time passage is expressed by, for example, an absolute time length from a predetermined reference point or a relative time length between two adjacent events.
The inventor of this invention has disclosed the comparison between the test pattern formation using the test data in the cycle based format and the test pattern formation using the test data in the event based format in the U.S. patent application Ser. No. 09/340,371. The inventor of this invention has also proposed an event based test system as a semiconductor test system as a new concept test system. The details of the structure and operation of the event based test system is given in the U.S. patent application Ser. No. 09/406,300 owned by the same assignee of this invention.
As described in the foregoing, in the semiconductor test system, a large number of printed circuit boards and the like which is equal to or greater than the number of the test pins are provided, resulting in a very large system as a whole. In the conventional semiconductor test system, the printed circuit boards and the like are identical to one another.
For example, in a high speed and high resolution test system, such as a test rate of 500 MHz and timing accuracy of 80 picosecond, the printed circuit boards for all the test pins have the same capabilities each being able to satisfy the test rate and timing accuracy. Thus, the conventional semiconductor test system inevitably becomes a very high cost system. Further, since the identical circuit structure is used in each test pin, the test system can conduct only limited types of test.
An example of devices to be tested includes a type of semiconductor device which has both an analog function and a digital function. A typical example of which is an audio IC or a communication device IC which includes an analog-digital (AD) converter, a digital-analog (DA) converter and a digital signal processing circuit. In the conventional semiconductor test system, only one type of functional test must be conducted at one time. Therefore, to test the mixed signal integrated circuit noted above, each functional block must be tested separately in a series fashion, such as, first testing the AD converter, then testing the DA converter, and after that, testing the digital signal processing circuit.
Even in the case where testing a device which is configured solely by logic circuits, almost always, not all of the pins of such a device under test require the highest performance of the semiconductor test system. For example, in a typical logic LSI device to be tested having several hundred pins, only several pins actually operate at the highest speed and require the highest speed test signal while other several hundred pins operate at substantially lower speed and require low speed test signals. This is also true to a system-on-chip (SoC), a recent semiconductor device which draws high attention. Thus, high speed test signals must be applied to only a small number of pins of SoC while low speed test signals are sufficient for other pins.
Since the conventional semiconductor test system cannot conduct different types of test in parallel at the same time, it has a drawback that, to complete the mixed signal device test, it requires a long time. Further, the high performance which is needed only for a small number of pins of the device under test is equipped to all of the test pins, resulting in the high cost of the test system.
One of the reasons that the conventional semiconductor test system installs the identical circuit configuration in all of the test pins as noted above, and as a result, are not able to conduct two or more different kinds of test at the same time by having different circuit configuration, is that the test system is configured to generate the test pattern by using the cycle based test data. In producing the test pattern using the cycle based concept, the software and hardware tend to be complicated even when using the same circuit configuration for all the test channels. Thus, it is practically impossible to include different circuit configurations in the test system because it would make the test system and associated software even more complicated.
To explain the above noted reason more clearly, brief comparison is made between the test pattern formation using the test data in the cycle based format and the test pattern formation using the test data in the event based format with reference to waveforms shown in FIG. 3. The more detailed comparison is disclosed in the above noted U.S. patent applications owned by the same assignee of this invention.
The example of FIG. 3 shows the case where a test pattern is created based on the data resulted from the logic simulation conducted in the design stage of the integrated circuit and stored in a dump file (VCD) 37. The output of the dump file is data in the event based format showing the changes in the input and output of the designed LSI (large scale integrated circuit) device and having descriptions 38 shown in the lower right of FIG. 3 for expressing, for example, the waveforms 31.
In this example, it is assumed that test patterns such as shown by the waveform 31 are to be formed by using such descriptions. The waveforms 31 illustrate test patterns to be generated by pins (tester pins or test channels) Sa and Sb, respectively. The event data describing the waveforms is formed of set edges San, Sbn and their timings (for example, time lengths from a reference point), and reset edges Ran, Rbn and their timings.
For producing a test pattern to be used in the conventional semiconductor test system based on the cycle based concept, the test data must be divided into test cycles (tester rate), waveforms (types of waveforms, and their edge timings), and vectors. An example of such descriptions is shown in the center and left of FIG. 3. In the cycle based test pattern, as shown by waveforms 33 in the left part of FIG. 3, a test pattern is divided into each test cycle (TS1, TS2 and TS3) to define the waveforms and timings (delay time) for each test cycle.
An example of data descriptions for such waveforms, timings and test cycles is shown in timing data (test plan) 36. An example of logic xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d or xe2x80x9cZxe2x80x9d of the waveforms is shown in vector data (pattern data) 35. For example, in the timing data 36, the test cycle is described by xe2x80x9cratexe2x80x9d to define time intervals between test cycles, and the waveform is described by RZ (return to zero), NRZ (non-return to zero) and XOR (exclusive OR). Further, the timing of each waveform is defined by a delay time from a predetermined edge of the corresponding test cycle.
As in the foregoing, because the conventional semiconductor test system produces a test pattern under the cycle based procedure, the hardware structures in the pattern generator, timing generator, and wave formatter tend to be complicated, and accordingly, the software to be used in such hardware also becomes complicated as well. Further, since all of the test pins (such as Sa and Sb in the above example) are defined by the common test cycle, it is not possible to generate test patterns of different cycles among the test pins at the same time.
Therefore, in the conventional semiconductor test system, the same circuit configurations are used in all of the test pins, and it is not possible to incorporate printed circuit boards of different circuit structures therein. As a consequence, it is not possible to perform different test such as the analog block test and the digital block test at the same time in a parallel fashion. Moreover, for example, a high speed type test system also needs to include a low speed hardware configuration (such as high voltage and large amplitude generation circuit and a driver inhibit circuit, etc.), the high speed performance cannot be fully improved in such a test system.
In contrast, for producing a test pattern by using the event based method, it is only necessary to read set/reset data and associated timing data stored in an event memory, requiring very simple hardware and software structures. Further, each test pin can operate independently as to whether there is any event therein rather than the test cycle, thus, test patterns of different functions and frequency ranges can be generated at the same time.
As noted in the foregoing, the inventors of this invention have proposed the event based semiconductor test system. In the event based test system, since the hardware and software involved are very simple in the structure and contents, it is possible to formulate an overall test system having different hardware and software therein. Moreover, since each test pin can operate independently from the other, two or more tests which are different in functions and frequency ranges from one another can be carried out in a parallel fashion at the same time.
Therefore, it is an object of the present invention to provide a semiconductor test system which has tester modules of different capabilities corresponding to test pins and thus is capable of testing a mixed signal device under test by testing the analog function and the digital function in parallel at the same time.
It is another object of the present invention to provide a semiconductor test system in which tester modules of different pin numbers and capabilities can freely installed in a tester main frame (or test head) and in which specification for connection between the tester modules and the tester main frame is standardized.
It is a further object of the present invention to provide a semiconductor test system which can freely accommodate a plurality of tester modules of different capabilities, thereby testing a plurality of different kinds of devices or functional blocks under test in parallel at the same time.
It is a further object of the present invention to provide a semiconductor test system which can freely accommodate a plurality of tester modules of different capabilities, thereby establishing a test system having a sufficient test performance with low cost, and further enabling to improve its capability in the future.
The semiconductor test system of the present invention includes two or more tester modules whose performances are different from one another, a test head to accommodate the two or more tester modules having different performances, means provided on the test head for electrically connecting the tester modules and a device under test, an optional circuit corresponding to the device under test when the device under test is a mixed signal IC having analog and digital functions, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus. One type of the performances of the tester module is a high speed and high timing resolution while other type of performance is a low speed and low timing resolution.
In the semiconductor test system of the present invention, each of the tester modules includes a plurality of event tester boards. Under the control of the host computer, each tester board provides a test pattern to a corresponding pin of the device under test and evaluates a resultant output signal from the device under test.
Since the semiconductor test system of the present invention has a modular structure, a desired test system can be formed freely depending on the kind of devices to be tested and the purpose of the test. Thus, when the device under test is a mixed signal integrated circuit (having both an analog circuit and a digital circuit therein), the analog circuit and the digital circuit can be tested in parallel at the same time. When the device under test is a high speed logic IC, only a small portion of the logic circuits therein are actually operating in the high speed. Thus, for testing such a high speed logic IC, a small number of tester pins have to have high speed capability. In the semiconductor test system of the present invention, the specification for connecting the test head and tester modules (interface) is standardized. Accordingly, any tester modules having the standard interface can be installed at any positions in the test head.
As noted above, in the semiconductor test system of the present invention, the tester module (tester board) is configured by event based architecture where all the information required for executing the test is prepared in the event based format. Therefore, the rate signal showing the start timing of each test cycle or the pattern generator which operates in synchronism with the rate signal used in the conventional technology are no longer necessary. Because it is not necessary to include the rate signal or pattern generator, each test pin in the event based test system can operate independently from the other test pins. Therefore, different types of test, such as analog circuit test and digital circuit test can be performed at the same time.
Further, because of the event based architecture, the hardware of the event based test system can be dramatically reduced while the software for controlling the tester modules can be dramatically simplified. Accordingly, an overall physical size of the event based test system can be reduced, resulting in further cost reduction, floor space reduction and associated cost savings.
Further in the semiconductor test system of the present invention, the logic simulation data in the design stage of the device in the electronic design automation (EDA) environment can be directly used to produce the test pattern to test the device in the evaluation stage. Thus, a turnaround time between the design of the device and the evaluation of the device can be substantially decreased, thereby further decreasing the test cost while increasing the test efficiency.